今天研究了IDE控制器的设置,把NW9440和T60的IDE控制器设置参数做了个对比,发现HP果然在这里做了限制。NW9440和T60的控制器配置如下图。 其中最后4处标红的地方与UDMA设置有关。不知道哪位高人会修改南桥寄存器的值,如果能把这4个值修改掉,估计就能解决硬盘限速的问题。
关于这些值的解释,摘要如下:
15.1.20 IDE_TIMP — IDE Primary Timing Register bit3
Drive 0 DMA Timing Enable (DTE0) — R/W.
0 = Disable
1 = Enable fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data port will run in compatible timing.
其中关于“fast timing mode”的说明如下:
5.16.2.2 Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster than its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI clock and no more transfers take place until DMA request is asserted again.
15.1.23 SDMA_CNT—Synchronous DMA Control Register
bit0
Primary Drive 0 Synchronous DMA Mode Enable (PSDE0) — R/W.
0 = Disable (default)
1 = Enable Synchronous DMA mode for primary channel drive 0.
其中关于“Synchronous DMA mode”的说明如下
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to two IDE devices (one device on Ultra Mobile) providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up 100 MB/sec. It does not consume any legacy DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers.
15.1.24 SDMA_TIM—Synchronous DMA Timing Register
bit1:0
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also determined by the setting of these bits. 15.1.25 IDE_CONFIG—IDE I/O Configuration Register
bit4
Primary Master Channel Cable Reporting — R/W. BIOS should program this bit to tell the IDE driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
[ Edited by wertpoiu on 2011-10-6 01:39 ] |